The present invention relates to a magnetic bubble memory device using a magnetic bubble chip with major-minor structure, and more particularly to a method of allocating logical addresses in which the amount of hardware and software necessary to control addressing can be reduced.
In a magnetic bubble memory device using a magnetic bubble chip with major-minor structure, that is, a magnetic bubble chip provided with a plurality of minor loops for storing information and a major loop for reading and writing (or a major line only for reading and another major line only for writing), an address is determined by a bit position on each of the minor loops. In such a magnetic bubble memory device, logical addresses on each minor loop are usually allocated at intervals of a predetermined number of bits, in order to shorten an access time necessary to read out or to write in consecutive addresses.
An example of such address assignment will be explained below.
In case of data retrievel, bubbles to be read are replicated to the read line by a replicator which connects the minor loops to the read major line, in parallel from the major lines. And then, those replicated bubbles are propagated to a bubble detector on the read major line. Bubbles next to be read cannot be replicated to the read major line while the replicated bubbles corresponding to a current address are being propagated on the replicator portion of the read major line. During the bubble propagation on the read major line, all the bubbles in each minor loop are simultaneously propagated along that minor loop. Accordingly, logical address are assigned at interval of m bits so that the bubbles at the next logical addres can reach the replicator portion in the minor loop, when the last bubble of the replicated bubble stream corresponding to the current logical address has passed through the replicator portion in the read major line. In order to make possible such allocation of logical addresses, it is required that the number m of bits indicating a distance between adjacent logical addresses is prime to the number n of bits of each minor loop.
On the other hand, the operation of magnetic bubbles is controlled on the basis of a physical bit position (that is, a physical address) on each minor loop. Accordingly, when logical addresses are assigned at intervals of m bits, it is necessary to translate (or convert) a logical address into a physical address. The logical to physical address conversion can be performed by the following two methods. In the first method, a logical address at the replicator or swap gates is calculated each time magnetic bubbles are propagated by one bit. In the case of the read operation, for example, the replicator is fired just when it is detected that the current physical address is equal to the one corresponding to the logical address of the target page.
In the second method, the number of bits to be propagated before driving the replicator or the swap gate is calculated from a physical address of stop position and the physical address corresponding to the logical address of the target page. In the case of the read operation, the replicator is fired just when the propagation is completed for the calculated number of bits. The physical address of stop position is also calculated from the physical address corresponding to the logical address of the last page when the operation is completed.
The first method is advantageous in that a logical address can be calculated through the addition indicated by the following equation (1), but has a drawback that such addition has to be performed each time magnetic bubbles are propagated by one bit. EQU l.sub.i+1 =l.sub.i .sym..sub.modulo n k (1)
where k indicates a constant which is determined on the basis of the numbers n and m, l.sub.i the logical address magnetic bubbles which are placed at the replicator before magnetic bubbles are propagated by one bit, and l.sub.i+1 the logical address of magnetic bubbles which are placed at the replicator after magnetic bubbles have been propagated by one bit. Further, the logical address is obtained by the following formula: EQU l=4.times.a+b
On the other hand, the second method is advantageous in that the logical to physical address conversion is made only at the beginning and end of an operation performed for a magnetic bubble chip, but has a drawback that multiplication and division are required in the calculation of address conversion.
In view of the above-mentioned, measures for performing the calculation of address conversion by an arithmetic logic unit (hereinafter referred to as an "ALU") to simplify a microprogram for executing the calculation, is described in an article entitled "The Development of a Bubble Memory Controller for Low-Cost File Use"(IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 1, February 1980, Page 25).
In this article, the number m of bits indicating a distance between adjacent logical addresses and the number n bits which each minor loop includes, are determined so as to satisfy the following equation: EQU n=4m-1 (2)
In this case, a physical address p corresponding to a logical address l can be calculated from the following equation (3) by using a quotient a and a remainder (namely, surplus) b which are obtained when l is divided by 4. EQU p=m.times.b+a (3)
The division of a numeral value by 2.sup.x (where x is a positive integer) can be performed by an ALU having a shift-right function (namely, a function of shifting each bit to the right), and therefore the use of such division in address conversion makes simple not only the circuit structure of ALU but also a microprogram for executing address conversion.
In the conventional example mentioned above, the calculation of address conversion can be readily performed on the basis of the equation (2), though the above division is not used. However, some useless addresses which are not accessed, are produced on each of minor loops which are provided on a magnetic bubble chip, and thus that area of the magnetic bubble chip which is occupied by the minor loops, is wastefully increased.